Principle VLSI/ ASIC Design Engineer

Join our team as a Principal VLSI/ASIC Design Engineer, where you will be responsible for the architecture, RTL design, implementation, and analysis of complex VLSI components and system-on-chip (SoC) solutions. You will lead early-stage ASIC architecture and design exploration, define architectural approaches, and drive RTL implementation. This role requires strong technical leadership, innovation, cross-functional collaboration, and the ability to mentor engineers while delivering high-quality, scalable, and production-ready designs.

• Lead the architecture, RTL design, implementation, and analysis of complex VLSI components and system-on-chip (SoC) solutions.
• Drive RTL implementation from architectural definition through synthesis, physical implementation support, timing closure, and production readiness.
• Conduct design reviews and evaluate product designs for compliance with architecture, implementation guidelines, quality standards, and industry best practices.

• The role requires strong technical leadership, innovation, cross-functional collaboration, and the ability to mentor engineers while delivering high-quality, scalable, and production-ready designs
• Demonstrated experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applications
• Experience leading architecture and design exploration through RTL implementation and product integration
• Design verification experience is not required but is highly desirable
• Typically, 9 + or more years of experience in ASIC, VLSI, SoC, or related hardware design
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be considered
• Proven ability to influence decisions across business units, functions, senior leadership, external partners, and industry organizations
• Is recognized as an internal authority in key ASIC, RTL, and VLSI technology areas
• Understanding of ASIC development flows, including architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoff
• Strong collaboration skills and experience working effectively across geographically distributed, cross-functional teams
• Provides technical leadership for major projects and programs and unites teams around common goals
• Ability to mentor engineers and provide technical direction without direct management responsibility
• Ability to evaluate design alternatives and make recommendations based on performance, power, area, cost, risk, and schedule
• Strong written and verbal communication skills, with the ability to explain complex technical concepts to both technical and executive audiences
• Demonstrated innovation, including the development or adoption of new technologies, methodologies, or design practices
• Strong analytical, problem-solving, and technical decision-making skills
• Ability to communicate architectural proposals, design plans, tradeoffs, risks, and results effectively
• Actively mentors engineers and contributes to the broader technical community
• Delivers unique, long-lasting improvements in areas such as time to market, product quality, cost reduction, scalability, and customer value
• Makes substantial technical contributions to significant HPE products, programs, or strategic architectural initiatives
• Experience with design modeling, simulation, performance analysis, and empirical evaluation methodologies
• Proven experience developing complex RTL using Verilog, System Verilog, or comparable hardware description languages
• Advanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC development
• Experience defining and improving design methodologies, tools, automation, and engineering practices
• Acts as a go-to creator and innovator for critical business and technology challenges
• Experience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architectures
• Experience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapaths
• Familiarity with formal verification, constrained-random verification, coverage methodologies, or verification planning
• Experience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologies
• Knowledge of industry standards and leading-edge ASIC implementation technologies
• Experience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers

USD 174,000 - 352,500