Physical Design Lead

Join Normal as a Physical Design Lead, where you will lead the end-to-end silicon realization path, optimize the full backend implementation flow, and drive physical optimization for power, performance, and area. You will collaborate closely with RTL, architecture, and DFT teams, execute full chip/block physical signoff checks, and support post-silicon physical debugging and bring-up. The ideal candidate has at least 7 years of managerial experience, a track record of successful tapeouts, and experience in AI or high-performance compute chip startups.

Lead the team responsible for the end-to-end silicon realization path, from synthesis and physical floorplanning to timing signoff and GDSII tapeout.

We are looking for a seasoned engineer and manager who thrives in cross-functional environments and takes pride in tapeout-proven execution

Responsibilities

• Drive the full backend implementation flow, optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS).
• Provide leadership to the Physical Design team, including hiring, individual guidance, and performance feedback, while creating work estimates and schedules to support aggressive tapeout plans.
• Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations
• Tapeout Track Record: Lead at least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes

Requirements

• The ideal candidate brings effective team building and leaders, and a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures
• PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure
• Managerial experience: at least 7 years experience in role
• Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility
• Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles
• Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration)
• Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows

Pay

USD 200,000 - 400,000