Verification Engineer

Riverlane, a leading quantum computing company, as a Verification Engineer. In this role, you will have end-to-end visibility across the entire stack, owning every aspect of verification and shaping how quality and reliability are built into our cutting-edge technology. You will work closely with designers and architects to define verification plans, develop and implement scalable testbenches, and maintain the health and evolution of the design verification environment. This is an exciting opportunity to be part of a talented team of hardware designers and embedded software engineers, and to learn about quantum computing along the way.

Responsibilities

• Proactively work with designers and architects to define verification plans based on design specifications.
• Develop and implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog.
• Maintain the health and evolution of the design verification environment, tracking of regressions, coverage metrics and bugs.

Requirements

• Exposure to different programming languages, such as C, C++ and Python

Knowledge of SystemVerilog assertion (SVA)

• A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback
• Ability to work effectively with ambiguity and changing requirements

Formal verification experience

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy
• Proven experience of testbench design with verification frameworks like UVM/OVM
• Experience debugging across RTL, simulation, and hardware
• A proactive person who can independently define the scope of work

Pay

GBP 60,000 - 88,000