Senior FPGA Engineer (Systems Team)
Riverlane
- Cambridge, United Kingdom
- Senior Level
- PhD or doctorate
- Posted
Skills
Required
- UVM verification environment
- Python
- C++
- SystemVerilog / VHDL
- FPGA platforms
- AMD / Xilinx
- MPSoCs / RFSoCs / Altera
- Stratix 7 / Stratix 10
- quantum mechanics
Preferred
- FPGA
- decoders
- LDPC / turbo codes
- Ethernet
Join Riverlane, a leading quantum computing company, as a Senior FPGA Engineer. In this role, you will work on configuring and adapting Riverlane's Deltaflow Hardware to connect quantum computers and support scientists in running quantum experiments. You will also have the opportunity to collaborate with mathematicians, physicists, and engineers on various projects related to quantum error-correcting algorithms. This position offers equity, generous annual leave, private medical insurance, life insurance, and a contributory pension scheme.
Responsibilities
- Configurer le matériel Deltaflow de Riverlane pour connecter les ordinateurs quantiques et fournir des systèmes à faible latence et à haut débit.
- Écrire du RTL pour s'adapter aux systèmes de contrôle des clients et garantir que les paquets de données sont reçus correctement.
- Collaborer avec l'équipe d'application quantique de Riverlane pour concevoir des expériences afin de tester le système.
Requirements
- A curious nature and a passion for learning and continuous improvement
Experience working on scientific instrumentation
- Proven capability to test, debug, and improve a UVM verification environment
- Excellent communication skills and the ability to work independently and collaboratively as part of a team
- Ability to convert product requirements into technical specifications and document and share your work
- Good knowledge of Python and C++
- Experience writing SystemVerilog or VHDL
- A PhD in a relevant subject
- Experience with state-of-the-art FPGA platforms, such as AMD/Xilinx MPSoCs/RFSoCs or Altera Stratix 7 or Stratix 10
- Good knowledge of quantum mechanics
Preferred
- Proven professional experience in at least one of the following areas: implementing modern classical decoders on FPGA (e.g., LDPC or turbo codes); implementing Ethernet and high-speed protocols; or implementing custom protocols and standards
Pay
GBP 70,000 - 108,000
