Junior Emulation Engineer

Junior Emulation Engineer to join our pre-silicon verification team. This is an excellent opportunity for recent graduates and early-career engineers to build hands-on experience bringing up complex SoC designs on hardware emulation platforms.

About Celero Communications, Inc.

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure. We recently announced a $275M Series C following the validation of the industry’s first 2nm coherent DSP silicon. Bloomberg also reported that Alphabet’s CapitalG has backed Celero at a $3B valuation. As we continue to grow, we’re hiring exceptional talent across the United States, Canada, and Argentina for a variety of exciting opportunities.

Responsibilities

• In this role, you will help compile, run, and debug RTL on emulation systems, supporting early validation of hardware and firmware ahead of tape-out.
• You will work closely with RTL design, verification, and firmware teams, learn from senior engineers, and grow into an independent contributor on next-generation semiconductor products.
• Emulation Bring-Up: Support compilation, partitioning, and bring-up of RTL designs on hardware emulation platforms.
• Environment Support: Assist in building and maintaining emulation environments, including testbenches, transactors, and run configurations.
• Debug & Triage: Analyze waveforms, logs, and traces to isolate failures, and work with RTL and verification engineers to root-cause issues.
• Automation: Develop and maintain scripts in Python, Tcl, Perl, or shell to automate builds, regressions, and reporting.
• Firmware & Software Enablement: Help run pre-silicon firmware and software workloads on emulation to validate functionality before silicon.
• Documentation & Growth: Document findings, flows, and best practices, and actively learn emulation methodologies from senior team members.

Requirements

• Bachelor’s degree in Electronic, Electrical, or Computer Engineering (or a related field), completed or expected within the next 6–12 months.
• 0–2+ years of relevant experience; internships, thesis work, and academic or personal projects in digital design, verification, or FPGA are welcome.
• Solid understanding of combinational and sequential logic, FSMs, clock domains, and basic timing concepts.
• Working knowledge of Verilog/SystemVerilog; able to read RTL and debug simple design or testbench issues.
• Basic proficiency in Python, Tcl, Perl, or shell scripting, and comfort working in a Linux command-line environment.
• Professional English (written and spoken) for collaboration with global teams.

Preferred

• Exposure to emulation or FPGA prototyping tools (e.g., Cadence Palladium/Protium, Synopsys ZeBu, Siemens Veloce, Vivado/Quartus), UVM or SystemVerilog assertions, SoC basics (AXI/AMBA, ARM/RISC-V, DDR, PCIe), and Git or CI tools.

This is an on-site position. Qualified candidates must be willing to relocate to Cordoba.