Principal Physical Verification Engineer

Responsibilities

• Team & Project Leadership
• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks
• Physical Verification Ownership
• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Participate in tapeout readiness reviews

Preferred

• Able to assemble a flow to support block/chip level PV
• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

Key Responsibilities

• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules

Cross-Functional Collaboration

Partner with analog, block, chip top owners to ensure clean floorplan

Provide early guidance on corner case requirements

Influence floorplan constraints, hierarchy, and implementation strategy

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications

Proven hands-on experience with

Physical Verification tools (Synopsys IC Validator (ICV), Siemens Calibre)

Strong expertise in

Floorplanning to avoid DRC/LVS issues

Provide guidance to analog IP team to allow for clean integration

Preferred Qualifications

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)