- California, United States
- Mid Level
- Posted
Responsibilities
- RTL Synthesis, Constraint writing, validation, Static timing
- Analysis Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA Debug synthesis issues and STA Generate clean netlist.
Requirements
- Design Engineer with very strong experience Timing Constraints Writing.
- RTL to Physical Design (RTL2PD) stage experience RTL2PD Design Engineer(ASIC) MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing
- Experience: 8–12 years of hands-on RTL Synthesis EDA exposure: Design compiler, PrimeTime, Tempus, Genus, Multi-Node Design: Experience working with 16nm, 7nm… etc nodes
