Staff Design Engineer

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Lattice is looking for a motivated and experienced Staff Design Engineer to integrate and productize USB IP and subsystems for next-generation FPGA products. The role focuses on USB 2.0 and USB 3.x controller and PHY integration, spanning subsystem validation, software enablement, silicon bring-up, and collaboration across Design, DV, Software, Applications, and external IP partners.

Key Responsibilities Own the integration of USB controller and USB PHY IP into the FPGA subsystem, including digital interfaces, configuration paths, clock/reset connectivity, and integration requirements. Define and implement the subsystem-level RTL, wrappers, adapters, control logic, and configuration interfaces required to integrate USB controller and PHY IP.

Work with Design Verification teams to define integration test plans and validate end-to-end USB subsystem behavior through simulation, emulation, FPGA prototyping, coverage closure, and pre-silicon debug. Drive subsystem-level root-cause analysis across USB controller-to-PHY interaction, integration RTL, software or firmware configuration, interoperability, compliance, and silicon behavior.

Work with software and firmware teams to define and validate USB configuration, feature enablement, diagnostics, enumeration, initialization, and user-flow requirements. Integrate and review DFT and DFD requirements for the USB subsystem, including testability, debug observability, silicon bring-up, and production-test considerations.

Work with third-party suppliers of USB controller and PHY IP to clarify interface and configuration requirements, review deliverables, and resolve integration, verification, and silicon issues. Develop and maintain USB subsystem integration specifications, interface requirements, configuration documentation, and bring-up guidelines.

Support integrated USB subsystem bring-up, laboratory debug, protocol analysis, compliance and interoperability testing, and customer issue resolution; document findings and drive assigned issues to closure. Identify engineering activities that can benefit from AI assistance, and propose, develop, and deploy practical AI-assisted workflows for design, verification, debug, data analysis, and technical documentation.

Participate in design reviews and quality checks, and contribute to continuous improvement of design and debug methodologies. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. Typically 8+ years of semiconductor, ASIC, SoC, or FPGA design experience.

Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations. Strong experience with USB 2.0 or USB 3.x controller, protocol, subsystem integration, or related USB PHY technology.

Experience working with Design Verification teams and debugging pre-silicon design or integration issues using simulation, emulation, or FPGA prototyping environments. Experience supporting silicon bring-up, laboratory debug, interoperability, or customer issue resolution.

Experience working with DFT or DFD methodologies, including testability, debug observability, scan/ATPG, silicon bring-up, or production-test considerations. Demonstrated experience identifying opportunities, proposing, developing, and implementing AI-assisted engineering workflows to improve design and integration productivity, technical investigation, debug, data analysis, and documentation.

Strong technical communication and collaboration skills across engineering disciplines. Preferred Qualifications Experience with USB protocol operation and debug, including enumeration, link state transitions, power management, error recovery, and compliance or interoperability testing.

Experience with USB controller-to-PHY interfaces and specifications, such as UTMI/UTMI+, ULPI, PIPE, or related integration interfaces. Experience with SerDes-based protocols or high-speed serial interfaces, including protocol architecture, controller-to-PHY integration, link bring-up, or system-level debug.

Understanding of USB PHY and mixed-signal behavior, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up. Direct analog circuit design experience is not required. Experience integrating third-party USB controller or PHY IP and working with external IP suppliers on requirements, deliverables, integration, verification, or silicon issues.

Familiarity with physical-design interfaces such as synthesis, LEC, static timing analysis, or timing closure. Experience with design-quality methodologies such as Lint, CDC, RDC, low-power/UPF, or related structural checks. Knowledge of firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.

Exposure to USB compliance, interoperability, package, board, signal-integrity, connector, or platform-level considerations. #LI-DNP Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: Malaysia Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.

Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.

Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter, Facebook, or RSS.

At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.