CAD RTL/FE Manager

• As a manager in the RTL/FE CAD team, you have the opportunity to shape the future of chip design and impact Apple engineers who develop the next generation of Apple products! You will lead a high-impact team that develops software solutions used by thousands of RTL design and integration engineers globally across all chip families (iPhone, iPad, Mac, Apple Watch, and more).
• In this role, you will be a key catalyst in transforming front-end hardware design into a modern, agile discipline. You will spearhead the transition to agentic workflows—redefining how RTL and integration teams operate in the AI era. This role combines deep knowledge of RTL/FE flows with modern software engineering practices, people leadership, and a transformative vision for engineering methodology.

## Description

• You will lead, grow, and inspire a team of engineers driving critical tools across the RTL/FE space, including RTL connectivity, SoC assembly, static sign-off checks (Lint, CDC, RDC), cloud-native services, and CI/CD pipelines.
• Beyond delivering core CAD solutions, you will champion a strategic shift toward agentic design flows. You will guide your team and partner organizations in adopting agile, iterative design practices powered by autonomous agents and AI-assisted tooling. Your work will directly redefine engineering methodologies—accelerating design velocity, eliminating manual bottlenecks, and establishing new standards for quality and sign-off readiness. Prior hands-on experience and proven leadership in agentic systems, AI-augmented engineering, or agile hardware transformation will be essential in navigating this shift.

## Minimum qualifications

• 7+ years of experience as a people manager leading engineering teams.
• BSc/MSc in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Proven track record in RTL design, design integration, or RTL/FE CAD across complex SoC projects.
• Strong software engineering foundation, including system architecture, algorithms, data structures, and modern software design principles.
• Demonstrated experience driving workflow automation, process modernization, or agile transformation within hardware/CAD environments.
• Outstanding communication, collaboration, and stakeholder management skills with the ability to influence cross-functional technical direction.
• Solid grasp of the front-end chip design flow: SystemVerilog/Verilog, RTL integration, static checks (Lint, CDC, RDC), synthesis, and simulation.

## Preferred qualifications

• Prior expertise designing, deploying, or evaluating agentic workflows, LLM harnesses, or AI-assisted development tools in hardware design or software engineering.
• Experience pioneering agile methodologies in silicon design (e.g., continuous integration for hardware, rapid iteration cycles, automated regressions).
• Hands-on experience with production RTL connectivity tools and SoC top-level assembly flows.
• Strong modern Python expertise (AsyncIO, FastAPI, Pydantic, SQLAlchemy) and experience building distributed, cloud-native backend services.
• Proven success managing relationships with major EDA vendors and driving large-scale tool adoption.