Senior Principal Engineer (Network Modeling Lead)

Astera Labs as a Senior Principal Engineer (Network Modeling Lead) and take ownership of the performance models that shape our fabric. In this high-impact role, you will work at the intersection of architecture, performance analysis, and software, influencing the next generation of products and enabling informed architectural decisions.

Responsibilities

• You will design, implement, and maintain features in AI/ML system simulators and fabric models, continuously calibrating and validating models against benchmark data.
• You will also proactively identify architectural bottlenecks and propose solutions, serving as the internal authority on fabric modeling.
• Posséder les modèles de performance qui façonnent le tissu, quantifiant les plafonds de bande passante, de latence et de débit, et prédisant le comportement du matériel.
• Concevoir, mettre en œuvre et maintenir des fonctionnalités dans des simulateurs de systèmes AI/ML et des modèles de tissu, en améliorant la fidélité, l'évolutivité et les performances d'exécution.
• Identifier proactivement les goulets d'étranglement architecturaux qui ne se manifesteraient autrement qu'à grande échelle et proposer des solutions dans le modèle de réseau interne.
• Solid understanding of high-speed interconnect and switching fundamentals, including the physical layer, and protocols such as PCIe (Gen 6/7), ESUN, UEC or UALink
• Hands-on experience with cycle-approximate or event-driven system modeling and simulation
• Deep experience designing, enhancing, and maintaining fabric models using established frameworks such as Astera-Sim, Garnet, NS-3, ATLAHS, BookSim, or in-house simulators

Requirements

• Strong programming skills in Python and/or C++ for building and analyzing system models
• 12+ years of relevant background in network modeling, system architecture, and scaleup fabric benchmarking and analysis
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Experience characterizing performance across bandwidth, latency, buffering, and congestion in network model or cluster
• MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science
• Background correlating models against emulation or silicon measurements, and analyzing competitive or emerging fabric architectures
• Strong communication skills with a track record of influencing architectural decisions and contributing to IP/patents

Preferred

• Familiarity with AI/ML collective communication (AllReduce, AllGather, ReduceScatter) and large-scale LLM training/inference traffic patterns

Pay

USD 205,000 - 260,000