SiP System and Design Architect (m/f/d)

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About Aumovio

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• Since its spin-off in September 2025 AUMOVIO continues the business of the former Continental group sector Automotive as an independent company.
• The technology and electronics company offers a wide-ranging portfolio that makes mobility safe, exciting, connected, and autonomous.
• This includes sensor solutions, displays, braking and comfort systems as well as comprehensive expertise in software, architecture platforms, and assistance systems for software-defined vehicles.
• In the fiscal year 2024 the business areas, which now belong to AUMOVIO, generated sales of 19.6 billion Euro.
• The company is headquartered in Frankfurt, Germany and has about 87.000 employees in more than 100 locations worldwide.

Responsibilities

• The SiP System and Design Architect (m/f/d) is responsible for following tasks: Translating product and use-case requirements into executable SiP functional architectures, chip or chiplet partitions and package-level design concepts SiP floorplanning, die-to-die communication concepts, substrate electrical architecture and package-board interfaces System-level concepts covering performance, dataflow, timing, boot, power management, functional safety, cybersecurity interfaces, testability, redundancy and repair
• Setting up virtual architecture models that enable early performance assessment and design-space exploration before physical implementation
• Maintaining architecture specifications, interface definitions, design constraints and cross-domain alignment between system, silicon, software, package, test and manufacturing stakeholders
• Representing AUMOVIO in relevant external industry associations, consortia and collaborative research programs and for transferring applicable results, requirements and ecosystem developments into internal SiP architecture activities
• Capturing and analyzing product requirements, workloads, interfaces, safety goals, timing constraints, power targets, package limitations, and cost assumptions
• Developing alternative chip and chiplet partitioning concepts and evaluate functional allocation, dataflow, latency, bandwidth, power, reuse, supply risk and scalability
• Creating SystemC and Transaction-Level Modeling based executable models for architecture exploration, performance assessment and interface evaluation
• Defining die-to-die interface requirements and protocol concepts, including bandwidth, latency, coherency, link initialization, monitoring, error handling and interoperability constraints
• Developing preliminary SiP floorplans covering die placement, interface proximity, routing resources, power distribution, thermal constraints, keep-out regions and test access
• Defining the package electrical architecture, including substrate stack-up requirements, high-speed routing constraints, power-delivery concepts, grounding and decoupling strategy
• Developing architecture concepts for boot, power sequencing, clocking, reset, diagnostics, functional safety, cybersecurity interfaces, redundancy and repair
• Defining design for test, design for manufacturability, design for reliability and system-level test requirements together with the respective experts and external partners
• Coordinating architecture trade-offs and design reviews with product, integrated-circuit, software, package, simulation, test, safety, security and supplier stakeholders
• Maintaining architecture documents, interface specifications, assumptions, verification criteria, technical risks and reusable SiP design guidelines
• Knowledge of boot, clock, reset, power management, diagnostics, functional safety, cybersecurity interfaces, redundancy and repair concepts
• Motivation and Inspiration Team player and contributes towards team goals

Requirements

• Academic degree in Electrical Engineering, Microelectronics or comparable qualification In-depth experience in semiconductor technology Long-term experience in IC design methodology and EDA tools
• Several years of experience in System-on-Chip, multi-die, System-in-Package or complex embedded-system architecture In-depth experience in system architecture, chip partitioning, performance modeling, interface definition and hardware/software co-design
• Profound Experience with SystemC, Transaction-Level Modeling or comparable virtual prototyping and architecture exploration methods
• Deep Knowledge of high-speed die-to-die and package interfaces (like with Universal Chiplet Interconnect Express - UCIe), protocol concepts, signal and power integrity constraints and substrate design fundamentals
• Experience with package or substrate floorplanning, electrical package design, layout constraints and design-rule handover preferred
• Experience in design for test, system-level test concepts and requirements engineering for automotive electronics preferred
• Business fluent English language skilles (written and spoken), German language skills preferred
• Initiative - self-confident, taking ownership and acting proactively
• Ability to learn continuously by being open and flexible to new tasks/fields
• Good Communication skills
• Customer focus - anticipating and understanding the customers' needs

Benefits

• Next to the interesting daily work the region around Regensburg is offering a high recreational value and quality of life.
• Profit from extensive benefits at the location such as different canteens and cafeterias, a continuing education and training, health management, physiotherapy and much more.
• We offer an attractive salary as well as the possibility of hybrid and cross-border mobile work.
• For an improved work-life balance we support you with various initiatives for a better compatibility of family and career such as flexible work time model, part-time option, sabbatical, etc.
• You can expect a highly motivated team as well as diverse topics and projects in the global environment of the automotive industry.
• We are promoting lifelong Learning combined with personal and professional development.
• You are looking for an individual working time model?
• We support part-time work.