FPGA Design Verification Engineer
- El Segundo, United States
- Mid Level
- Posted
Responsibilities
- SystemVerilog and UVM testbench development
- C test development and hardware/software integration
- Test plan development, functional coverage, and coverage closure
- Universal Verification Component (UVC) development
- FPGA verification from test planning through tape-out
Requirements
- FPGA Design Verification
Preferred
- SpaceWire Protocol
- DDR4 Memory Interfaces
- SerDes Connectivity
- Configuration, Control, and Telemetry Systems