Principal ATE Test Engineer
- San Jose, United States
- Lead/Staff
- Bachelor's degree
- Posted
Skills
Required
- Ethernet
- Infiniband
- DDR
- USB
- ATE Platform
- communication/interface protocols
- PCI-Express
- Python
Preferred
- control interfaces
- I2C
- I3C
- SPI
- MDIO
- JTAG
- mixed signal SoC test program/hardware development
- SoC test
- mixed-signal silicon SoC
Join our team as a Principal ATE Test Engineer, where you will lead the development and support of complex mixed-signal silicon SoC products. You will be responsible for defining and implementing ATE programs, interacting with manufacturing partners, and overseeing the product from design to high volume production ramp. The ideal candidate will have a strong academic and technical background in electrical engineering, with at least 8 years of experience in releasing complex SoC/silicon products to high volume manufacturing.
Responsibilities
- Develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs.
- Lead ATE Test solutions for complex mixed-signal silicon SoC products, ensuring product quality and compliance.
- Collaborate with design team to define test strategy, create and own test plan, and implement ATE patterns to optimize tester resources.
- The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp
- Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
- Expertise in production test of high speed SerDes operating at 16Gbps and higher
- Collaboration with design team to define test strategy, create and own test plan
- Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests
- Experience with lab equipment including protocol analyzers and oscilloscopes
Requirements
- The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc
Entrepreneurial, open-mind behavior and can-do attitude
- Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred
- ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing
- Strong team player with good communication skills to work alongside a team of high caliber engineers
- Professional attitude with ability to execute on multiple tasks with minimal supervision
- Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug
- Proficiency in, at least, one modern programming language such as C/C++, Python
- Tester platform selection, design, and development of ATE hardware for wafer sort and final test
- Experience with using Teradyne or Advantest 93k ATE platform
- Familiar with high-speed load board design techniques
- Experience in running External loopback at wafer sort
- Fluent in data processing using high level programming languages
- Familiarity with modern databases
- Basic knowledge of RF Testing on ATE Platform
Preferred
- Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc
- Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms
Pay
USD 209,000 - 240,000
