Senior Staff Engineer (CPU, Front-End Verification)

Join our team as a Senior Staff Engineer specializing in CPU front-end verification. In this role, you will focus on the unit-level verification of our RISC-V CPU front end, including instruction fetch, branch prediction, and surrounding fetch control structures. You will build testbenches, generate stimulus, and develop checkers for complex microarchitectural scenarios. This position offers the opportunity to gain practical experience with high-performance RISC-V fetch pipelines and prediction structures, as well as strategies for writing maintainable unit testbenches.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology

Responsibilities

• Contribuer à la vérification unitaire de l'avant du CPU RISC-V, y compris la récupération d'instructions et la prédiction de branches.
• Construire des bancs d'essai, générer des stimuli et développer des vérificateurs pour des scénarios microarchitecturaux complexes.
• Collaborer avec les concepteurs RTL pour tracer et corriger les erreurs de spécification, de redirection et de cas limites.
• C++ Integration: Help develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking
• Stimulus Generation: Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions
• Execution & Closure: Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified

Requirements

• Unit-Level Verification: Work within the front-end DV team to build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks