Digital Design Engineer (Tech Lead)
- San Jose, United States
- Lead/Staff
- 3+ years
- Bachelor's degree
- Posted
Skills
Required
- Ethernet
- SoC / silicon
- DFT
- RTL
- GDS
- PCIe
- Ualink
- Switch ASIC / Networking applications / Server / Storage
- Python
Preferred
- communication/interface protocols
- PCI-Express
Join our team as a Digital Design Engineer (Tech Lead) where you will be responsible for developing micro-architecture and implementing front-end circuit design for high-performance network controllers. You will have the opportunity to work with cutting-edge technology and make a significant impact in the field of digital design.
Concevoir et mettre en œuvre l'architecture micro-architecturale et le design de circuit avant, y compris RTL, synthèse, intégration IP et vérification.
Responsibilities
- Assurer la propriété au niveau du bloc, de l'architecture à GDS, et travailler sur la mise en service et le débogage du silicium.
- Collaborer avec les équipes de conception et de vérification pour garantir la conformité aux spécifications et aux normes de l'industrie.
- The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc
Requirements
- +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred
- Authorized to work in the US and start immediately
- Knowledge of design for test (DFT)
- Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc
- Silicon bring-up and debug experience
- Familiarity with UVM based design verification
- Block level ownership from architecture to GDS
- Experience with Synopsys and/or Cadence digital design tools/flows
- Small-geometry CMOS (≤28nm) design
- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc
- Scripting with Python or other equivalent programming languages
- Development/support for PCIe or Ethernet Switch products
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