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Principal Electrical Engineer (Smart Cable Modules)

Astera Labs

Skills

Required

  • SerDes
  • interfaces
  • Ethernet / PCIe / InfiniBand
  • electrical architecture
  • EDA tools
  • industry-standard schematic capture
  • Cadence
  • Allegro / OrCAD
  • PCB layout review
  • 56G / 112G
  • host-side switching
  • Python

Preferred

  • QSFP / OSFP
  • OIF
  • IEEE
  • copper cable / optical/pluggable module
  • high-speed
  • SerDes-based interconnect
  • lead hardware bring-up
  • mixed-signal

Join our team as a Principal Electrical Engineer, where you will take strategic ownership of our Smart Cable Module (SCM) hardware platform. In this senior individual-contributor role, you will define the electrical architecture of our next-generation active copper cable assemblies and pluggable modules. You will set design direction, establish engineering standards, and serve as the primary technical authority on module hardware across the full product lifecycle. You will collaborate with cross-functional teams, contract manufacturers, firmware teams, and hyperscale customers to deliver high-reliability products for data center AI/ML fabric and high-performance computing applications.

Definir y ser responsable de la arquitectura eléctrica de la plataforma de hardware de los módulos de cable inteligente, incluyendo la topología del canal SerDes y la estrategia de entrega de energía.

Responsibilities

  • Liderar el diseño y la captura de esquemas para módulos complejos de múltiples capas, incluyendo el diseño de entrega de energía y la gestión de la temperatura.
  • Colaborar con equipos multifuncionales para definir secuencias de inicialización, esquemas de gestión de energía y algoritmos de diagnóstico en tiempo real.
  • 10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products
  • Proven ability to lead hardware bring-up and debug complex mixed-signal failures using high-bandwidth oscilloscopes and protocol analyzers
  • Strong PDN design fundamentals: multi-rail sequencing, transient response, decoupling strategy, and thermal-electrical co-analysis
  • Hands-on experience with CMIS 5.x / SFF-8636 module management and I2C/MDIO interface design
  • Expert-level understanding of signal integrity principles - impedance control, differential pair management, eye mask budgeting, channel loss allocation - sufficient to author design rules and review layout without performing full SI simulation
  • Experience interfacing with silicon vendors/teams on customizing reference design, silicon errata management, and platform bring-up
  • Deep familiarity with OSFP, QSFP-DD800, and SFP-DD MSA mechanical, electrical, and management specifications
  • Experience with PCIe Gen 5/6 retimer module designs

Requirements

  • Proficiency with EDA tools: industry-standard schematic capture (Cadence Allegro / OrCAD) and PCB layout review
  • Demonstrated track record of architecting and delivering production hardware with 56G / 112G and faster SerDes interfaces (Ethernet, PCIe, or InfiniBand)
  • Bachelor’s or Master’s degree in electrical engineering or closely related field
  • Experience at the architecture or lead engineer level on 800G or beyond module programs
  • Working knowledge of host-side switching ASIC electrical interfaces and SerDes equalization schemes
  • Familiarity with co-packaged optics (CPO) or linear drive (LPO) module electrical architecture
  • Scripting fluency in Python for lab automation, measurement data reduction, or hardware characterization workflows

Preferred

  • Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies

Pay

USD 185,000 - 240,000