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ASIC DFT Technical Lead - MBIST

Cisco

Skills

Required

  • DFT
  • MBIST
  • SRAM circuit
  • memory Architecture
  • MBIST architecture
  • custom memory test algorithms
  • Vmin debug
  • post-silicon validation
  • memory failure analysis
  • controller design
  • Python / Perl / Tcl

Preferred

  • custom memory architectures
  • non-standard MBIST implementations
  • Mbist and memory testing architecture
  • ROMs
  • embedded memories
  • algorithms

About Cisco

  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
  • We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds.
  • These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
  • Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions.
  • Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless.
  • We work as a team, collaborating with empathy to make really big things happen on a global scale.
  • Because our solutions are everywhere, our impact is everywhere.
  • We are Cisco, and our power starts with you.

Responsibilities

  • Develop and optimize Mbist and memory testing architecture.
  • Lead the hardware implementation of defined architecture and methodology Develop and optimize MBIST controllers for SRAM, register files, ROMs, and custom embedded memories.
  • Define and implement standard and custom MBIST algorithms based on memory architecture and product requirements.
  • Collaborate with memory compiler and IP teams to understand memory internals and optimize test architecture.
  • Lead tape out sign-off for MBIST deliverables Debug Vmin-related memory failures and optimize test methodologies for low-voltage operation.
  • Lead post-silicon bring-up, memory diagnostics, and failure analysis.
  • Drive yield improvement by analyzing manufacturing test data and identifying systematic memory failures.
  • Support customer-returned devices through RMA debug and root-cause analysis.
  • Develop custom diagnostic algorithms for memories not supported by standard MBIST implementations.
  • Lead technical reviews across cross-functional teams.
  • Work closely with Design, Physical Design, Product Engineering, Reliability, and ATE teams to resolve silicon issues and improve product quality.

Requirements

  • The ideal candidate should have deep understanding on SRAM circuit, knowledge of memory Architecture, deep expertise in MBIST architecture, soft repair, hard repair, custom memory test algorithms, Vmin debug, post-silicon validation, yield improvement, and memory failure analysis.
  • Skills 12+ years of experience in DFT with strong focus on MBIST.
  • Expert knowledge of MBIST architecture and structural DFT methodologies.

Extensive experience with

  • MBIST controller design PSV and custom MBIST algorithms March algorithms and memory fault models BISR/BIRA Memory repair analysis
  • Deep understanding of SRAM, ROM, register files, and custom embedded memory architectures.

Strong expertise in

  • Vmin issue debugging Silicon bring-up Post-silicon validation Yield debug Failure analysis RMA debug
  • Proficiency in Verilog/SystemVerilog and scripting (Python, Perl, or Tcl).
  • Knowledge of IEEE 1149.1, IEEE 1500, and IEEE 1687.

Preferred

  • Experience with advanced process nodes (7nm, 5nm, 3nm, or below).
  • Strong background in custom memory architectures and non-standard MBIST implementations.
  • Proven experience leading DFT teams and driving silicon debug to production.
  • Excellent problem-solving, technical leadership, and cross-functional communication skills.

Equal opportunity

We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

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