Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Champion the integration of formal verification, and AI-driven coverage analysis.
• Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

Preferred

• Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.

Role Overview

Key Responsibilities: Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.

Required Qualifications

B.Tech/M.Tech in ECE with Experience in SystemVerilog/UVM and C/C++ for architectural modeling. Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.

Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations. We’re doing work that matters. Help us solve what others can’t.