Mixed-signal IC Design Engineer

Responsibilities

• Design, integrate, and deliver high-performance digital subsystems within mixed-signal ICs, enabling control, calibration, and high-speed data movement in analog-centric environments — owning the flow from RTL to physical implementation and tape-out.
• Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits — including calibration engines, control FSMs, data converters, and multiplexing logic.
• Contribute to the design of analog components at the digital-analog interface: calibration circuits, DACs/ADCs, comparators, and others.
• Integrate and customize external IP blocks (e.g., GPIOs, LVDS I/Os, serial interfaces), ensuring compliance with analog signal and timing requirements.
• Lead the digital implementation flow for mixed-signal blocks: from RTL to synthesis, floorplanning, P&R, timing closure, physical signoff, and tape-out.
• Collaborate closely with analog, layout, and system teams to co-optimize digital-analog boundaries, resolve cross-domain issues, and ensure robust high-speed performance.

Do great things

we deliver work we’re proud to sign our name to.

High velocity

speed matters. We move quickly, one step at a time.

One unit

• we’re all in this together, with relationships grounded in trust, respect, and camaraderie.
• Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.

Responsibilities

• Contribute to the development of high-speed serial I/O subsystems — experience in the design and implementation of SerDes blocks is a significant advantage.
• Language: English at a proficient level. French is a plus.

Required Skills and Experience

Strong experience in digital RTL design (Verilog/SystemVerilog), particularly for mixed-signal systems involving high-speed calibration/control loops, converters, multiplexers, and serial/parallel data paths.

Experience with analog IC development environments (Virtuoso or equivalent).

Deep understanding of digital-analog integration challenges, including timing closure, noise coupling, clock domain crossing, and analog-aware floorplanning in high-speed environments.

Proven ability to drive digital blocks from design through verification, synthesis, floorplanning, P&R, and tape-out, especially in the context of analog or RF ICs.

Skilled in integrating and adapting external IPs such as GPIOs, LVDS, SPI/I²C interfaces; experience with high-speed serializers/deserializers (SerDes) is a highly valued plus.

Proficient with industry-standard EDA toolchains for both front-end (design/verification) and back-end (physical implementation), with a strong grasp of mixed-signal layout constraints.

Pay and benefits

• Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.
• Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).
• Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.
• Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.
• Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.
• Reimbursement of 50% of the public transport subscription fee.
• A high-paced, multicultural (with 9 nationalities), and engineering-led environment.