Layout Scale-Up Engineer

Responsibilities

• You'll build the layout infrastructure that makes that scaling possible — PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation. This is a semiconductor physical-design role applied to superconducting hardware, not a quantum physics one.
• Build and own the PDK — layer stack, technology file, parametric cells (junctions, CPW, resonators, couplers, pads, airbridges/crossovers) — and their DRC/LVS decks
• Design a tile-based, hierarchical layout methodology: standardized reticle-compatible tiles, programmatic instantiation, and stitching for wafer-scale and multi-chip designs
• Write and maintain layout generators (Python/GDS or vendor EDA scripting) that turn architecture spec + frequency plan into DRC-clean GDSII/OASIS with zero manual drawing
• Own mask generation end-to-end: floorplan → hierarchical layout → DRC/LVS/PEX signoff → wafer map, test structures, PCM placement → mask data prep and tape-out package
• Drive automation targets: >50% automated layout at 400 qubits, >80% at 1,000, >90% at 10,000+
• Keep DRC/LVS/PEX runtime and file size tractable at 10⁶–10⁸ elements via hierarchical, cell-level, and incremental verification
• Evaluate and deploy the EDA toolchain (Cadence/Siemens/Synopsys-class or open-source) and integrate it with EM-simulation handoff
• Serve as physical-implementation signoff at design review gates ahead of mask release

Requirements

• Fluent English and excellent written and verbal communication skills

About the Mission

Alice & Bob's current 48-qubit generation was hand-drawn — the next generations won't be. As we scale toward 1,000-, 10,000-, and eventually million-qubit chips, manual layout stops being an option: it doesn't scale, and it caps how fast we can iterate. This role exists to build the infrastructure — PDK, generators, automated flows — that lets chip complexity grow 10–1,000× while design cycle time stays flat.

Requirements

5+ years in physical design, custom/analog layout, PDK development, or mask data prep in a semiconductor context (CMOS backend, RF/analog, MEMS, or photonics), including at least one production tape-out owned end-to-end

Track record scaling a layout methodology — replacing hand-drawn layout with generators, PCells, or hierarchical flows on a design that grew substantially in element count

Hands-on parasitic extraction experience — commercial (Calibre xRC/xACT, Quantus, StarRC) and/or field-solver-based (FastCap/FastHenry, BEM/FEM) — including deck/rule-file development and correlation against EM or measurement

Strong layout-automation scripting: Python (gdstk/gdsfactory/KLayout API) and/or vendor languages (SKILL, Tcl)

Fluent in DRC/LVS deck authoring, GDSII/OASIS, reticle and stepper constraints (field size, stitching, alignment marks), and tape-out data prep

Comfortable turning a frequency plan or floorplan constraint set into geometry

Nice to Have

Experience with superconducting or cryogenic device layout (Nb/Ta/TiN/Al thin films, Josephson junctions, CPW resonators, airbridges) and the loss/crosstalk-driven layout rules that come with it

Recruitment Process

• Screening Call with Grace, Talent Acquisition Specialist (30 min)
• Hiring Manager Interview with Felix (45 min)
• Technical Interview/Presentation with the Team (120 min)
• Leadership Team Interview (30 min)
• Fit Interview (45 min)
• Reference check

Benefits

• Our success is your success: own it with our BSPCE plan
• Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.
• Flexible remote policy, up to 40 % a month
• A Parental plan including additional benefits such as crèche support or additional days-off to take care of under 12 years old children
• Subsidized membership with Urban Sports Club

Mental health support with moka.care

25-day vacation policy (as per French law) + RTT

Half of transportation cost coverage (as per French law), or yearly allowance for the die-hard bicycle users

Competitive health coverage, with Alan.

Meal vouchers with Swile, as well as access to a fully equipped and regularly stocked kitchen

French language courses covered by the company for those interested

Research shows that women might feel hesitant to apply for this job if they don't match 100% of the job requirements listed. This list is a guide, and we'd love to receive your application even if you think you're only a partial match. We are looking to build teams that innovate, not just tick boxes on a job spec.

You will join of one of the most innovative startups in France at an early stage, to be part of a passionate and friendly team on its mission to build the first universal quantum computer!

We love to share and learn from one another, so you will be certain to innovate, develop new ideas, and have the space to grow.